As represented by large-scale ASICs, the number of components per IC device, the functional complexity of IC devices and the miniaturization of IC devices have increasingly progressed in recent years to cope with the functional advancement and dimensional reduction of electronic devices.
The back surface of a wafer processed by semiconductor device fabricating processes is polished, and then the wafer is subjected to a dicing process to cut the wafer into pellets (referred to as “chips” or “IC chips”). The pellets are subjected to die bonding, wire bonding and packaging to fabricate a semiconductor device. The IC chip is electrically connected to a lead frame by a wire-bonding process.
Flip-chip bonding using bumps on IC chips has become prevalent in recent years. Flip-chip bonding is superior to wire bonding in respect of high-speed signal processing.
Flip-chip bonding is practiced in fabricating a nonpackaged bear-chip mount device having a bear IC chip mounted on a printed wiring board. It is difficult to handle such a bear-chip mount device. From the viewpoint of ensuring reliability, semiconductor IC packages with bumps are manufactured.
A method of fabricating chip-scale packages (CSPs), i.e., semiconductor IC packages with bumps, was recently proposed in “Chip Scale International 99”, SEM1, 1999. Specifically wiring lines and terminals (metal posts) are disposed on a wafer on which ICs are formed, the wafer is sealed in a resin to form a packaged wafer, bumps are formed on the packaged wafer, and the packaged wafer is cut into chip-scale packages, i.e., semiconductor IC packages.
A CSP thus fabricated is also called a wafer-level CSP (W-CSP).
A semiconductor device fabricated by such a semiconductor device fabricating method includes a semiconductor IC chip, metal posts formed on the semiconductor IC chip, a resin package packaging the semiconductor IC chip, and solder balls connected to the metal posts. The diameter of the metal post in the range of 100 to 200 μm must be about two-thirds the diameter of the solder balls, and the height of the metal posts is about 100 μm. Since the metal posts are thick and rigid, the resin package surrounding the metal posts is rigid. Thus, the metal posts are fixed firmly to the semiconductor IC chip.
When the semiconductor IC package (individual semiconductor device) mounted on a wiring board is subjected repeatedly to temperature change, a thermal stress is induced in the semiconductor IC package due to the difference Δα in thermal coefficient of expansion between the semiconductor IC package and the wiring board. Consequently, cracks develop in parts of the semiconductor IC chip around the metal posts, and cracks develop in the solder balls due to stress concentration on the joining parts of the metal posts and the solder balls.
The manufacturing cost of the W-CSP is not necessarily low.
The metal posts are formed by electroplating. Several hours are necessary to form the metal posts with a height of about 100 μm by electroplating, which increases the manufacturing cost. The process of packaging the wafer involves an expensive vacuum packaging apparatus of special construction.
The semiconductor IC package is subjected to burning and electrical characteristic tests. Minute, elastic structures, such as contact pins, are necessary to connect the semiconductor IC package electrically to a burn-in socket and test instruments with reliability for burn-in and electrical characteristic tests. Sockets for such a purpose are expensive.
Thus, it has been desired to develop measures for solving problems relating to the development of cracks in parts of the semiconductor IC chip around the metal posts and in the solder balls when the W-CSP mounted on a wiring board is subjected repeatedly to temperature change, and for reducing the manufacturing cost.